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ADS-932
16-Bit, 2MHz Sampling A/D Converters
INNOVATION and EXCELLENCE
FEATURES
* * * * * * * * * 16-bit resolution 2MHz sampling rate Functionally complete No missing codes over full military temperature range Edge-triggered 5V supplies, 1.85 Watts Small, 40-pin, ceramic TDIP 87dB SNR, -88dB THD Ideal for both time and frequency-domain applications
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INPUT/OUTPUT CONNECTIONS
FUNCTION +3.2V REF. OUT UNIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST DIGITAL GROUND FIFO/DIR FIFO READ FSTAT1 FSTAT2 START CONVERT BIT 16 (LSB) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION NO CONNECTION NO CONNECTION +5V ANALOG SUPPLY -5V SUPPLY ANALOG GROUND COMP. BITS OUTPUT ENABLE OVERFLOW EOC +5V DIGITAL SUPPLY DIGITAL GROUND BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
GENERAL DESCRIPTION
The low-cost ADS-932 is a 16-bit, 2MHz sampling A/D converter. This device accurately samples full-scale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-932 has been optimized to achieve a signal-to-noise ratio (SNR) of 87dB and a total harmonic distortion (THD) of -88dB. Packaged in a 40-pin TDIP, the functionally complete ADS-932 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The ADS-932 only requires the rising edge of the start convert pulse to operate. Requiring only 5V supplies, the ADS-932 dissipates 1.85 Watts. The device is offered with a bipolar (2.75V) analog input range or a unipolar (0 to -5.5V) input range. Models are available for use in either commercial (0 to +70C) or military (-55 to +125C) operating temperature ranges. A proprietary, auto-calibrating, error-correcting circuit enables the device to achieve specified performance over the full military temperature range. Typical applications include medical imaging, radar, sonar, communications and instrumentation.
10 FSTAT1 11 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 8 FIFO/DIR 9 FIFO/READ 29 BIT 1 (MSB) 28 BIT 1 (MSB) +3.2V REF. OUT 1 POWER and GROUNDING ANALOG GROUND DIGITAL GROUND +5V DIGITAL SUPPLY -5V SUPPLY +5V ANALOG SUPPLY NO CONNECTION 4, 36 7, 30 31 37 38 39, 40 ANALOG INPUT 3 S/H OFFSET ADJUST 5 OFFSET ADJUST CKT. 2-PASS ANALOG-TO-DIGITAL CONVERTER PRECISION +3.2V REFERENCE 27 BIT 2 26 BIT 3 25 BIT 4 CUSTOM GATE ARRAY 3-STATE OUTPUT REGISTER 24 BIT 5 23 BIT 6 22 BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB) 34 OUTPUT ENABLE 33 OVERFLOW
START CONVERT 12 EOC 32 COMP. BITS 35
TIMING AND CONTROL LOGIC
Figure 1. ADS-932 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2756 Fax: (508)339-6356 * E-mail:sales@datel.com * Internet: www.datel.com
ADS-932
ABSOLUTE MAXIMUM RATINGS
PARAMETERS +5V Supply (Pins 31, 38) -5V Supply (Pin 37) Digital Inputs (Pins 8, 9, 12, 34, 35) Analog Input (Pin 3) Bipolar Unipolar Lead Temperature (10 seconds) LIMITS 0 to +6 0 to -6 -0.3 to +VDD +0.3 5 -10 to +5 +300 UNITS Volts Volts Volts Volts Volts Volts C
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PHYSICAL/ENVIRONMENTAL
PARAMETERS Operating Temp. Range, Case ADS-932MC ADS-932MM Thermal Impedance jc ca Storage Temperature Range Package Type Weight MIN. 0 -55 -- -- -65 TYP. -- -- 4 18 -- MAX. +70 +125 -- -- +150 UNITS C C C/Watt C/Watt C
40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams)
FUNCTIONAL SPECIFICATIONS
(TA = +25C, VCC = 5V, +VDD = +5V, 2MHz sampling rate, and a minimum 3 minute warm-up unless otherwise specified.) +25C ANALOG INPUTS Input Voltage Ranges Unipolar Bipolar Input Resistance (pin 3) Input Resistance (pin 2) Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (-0.5dB) dc to 500kHz 500kHz to 1MHz Total Harmonic Distortion (-0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (w/o distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Signal-to-Noise Ratio (& distortion, -0.5dB) dc to 500kHz 500kHz to 1MHz Noise Two-Tone Intermodulation Distortion (fin = 200kHz, 240kHz, fs = 2MHz, -0.5dB) Input Bandwidth (-3dB) Small Signal (-20dB input) Large Signal (-0.5dB input) Feedthrough Rejection (fin = 1MHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to 0.001%FSR, 5.5V step) -- -- -- -- 83 82 79 78 -- -- -- -- -- -- -- -- 200 -90 -90 -88 -87 87 86 84 84 83 -89 7.8 7.1 90 77 +8 5 225 -81 -81 -80 -80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 83 82 79 78 -- -- -- -- -- -- -- -- 200 -90 -90 -88 -87 87 86 84 84 83 -89 7.8 7.1 90 77 +8 5 225 -81 -81 -80 -80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 80 76 76 -- -- -- -- -- -- -- -- 200 -88 -88 -85 -84 85 84 82 82 83 -89 7.8 7.1 90 77 +8 5 225 -80 -80 -78 -77 -- -- -- -- -- -- -- -- -- -- -- -- -- dB dB dB dB dB dB dB dB Vrms dB MHz MHz dB V/s ns ps rms ns -- -- -0.95 -- -- -- -- 16 16 1 0.5 0.1 0.1 0.1 0.1 -- -- -- +1.0 0.3 0.2 0.3 0.3 -- -- -- -0.95 -- -- -- -- 16 16 1.5 0.5 0.15 0.2 0.2 0.15 -- -- -- +1.0 0.5 0.4 0.5 0.5 -- -- -- -0.95 -- -- -- -- 16 16 2 0.5 0.5 0.5 0.4 0.5 -- -- -- +1.5 0.8 0.9 0.9 0.9 -- Bits LSB LSB %FSR %FSR %FSR % Bits +2.0 -- -- -- 40 -- -- -- -- 250 -- +0.8 +20 -20 -- +2.0 -- -- -- 40 -- -- -- -- 250 -- +0.8 +20 -20 -- +2.0 -- -- -- 40 -- -- -- -- 250 -- +0.8 +20 -20 -- Volts Volts A A ns MIN. -- -- 655 418 -- TYP. 0 to -5.5 2.75 687 426 10 MAX. -- -- -- -- 15 MIN. -- -- -- -- -- 0 to +70C TYP. 0 to -5.5 2.75 685 400 10 MAX. -- -- -- -- 15 -55 to +125C MIN. -- -- -- -- -- TYP. 0 to -5.5 2.75 685 400 10 MAX. -- -- -- -- 15 UNITS Volts Volts pF
2
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ADS-932
DYNAMIC PERFORMANCE (Cont.) Overvoltage Recovery Time A/D Conversion Rate ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Falling Edge of Enable to Output Data Valid Output Coding POWER REQUIREMENTS Power Supply Ranges +5V Supply -5V Supply Power Supply Currents +5V Supply -5V Supply Power Dissipation Power Supply Rejection
MIN. -- 2
+25C TYP. 250 --
MAX. 500 --
MIN. -- 2
0 TO +70C TYP. 250 --
MAX. 500 --
MIN. -- 2
-55 TO +125C TYP. MAX. 250 -- 500 --
UNITS ns MHz
3.15 -- --
+3.2 30 5
3.25 -- --
3.15 -- --
+3.2 30 5
3.25 -- --
3.15 -- --
+3.2 30 5
3.25 -- --
Volts ppm/C mA
+2.4 -- -- -- --
-- -- -- -- --
-- +0.4 -4 +4
+2.4 -- -- --
-- -- -- --
-- +0.4 -4 +4
+2.4 -- -- --
-- -- -- --
-- +0.4 -4 +4 10
Volts Volts mA mA ns
10 -- -- 10 -- -- Straight Binary, Complementary Binary, Complementary Offset Binary, Complementary Two's Complement, Offset Binary, Two's Complement
+4.75 -4.75 -- -140 -- --
+5.0 -5.0 +225 -135 1.85 --
+5.25 -5.25 260 -- 2.0 0.07
+4.75 -4.75 -- -140 -- --
+5.0 -5.0 +225 -135 1.85 --
+5.25 -5.25 260 -- 2.0 0.07
+4.9 -4.9 -- -140 -- --
+5.0 -5.0 +225 -135 1.85 --
+5.25 -5.25 260 -- 2.0 0.07
Volts Volts mA mA Watts %FSR/%V
Footnotes:
All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warm-up periods. The device must be continuously converting during this time. There is a slight degradation in performance when operating the device in the unipolar mode. When COMP. BITS (pin 35) is low, logic loading "0" will be -350A. A 1MHz clock with a positive pulse width is used for all production testing. See Timing Diagram for more details. 40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns Effective bits is equal to:
(SNR + Distortion) - 1.76 + 20 log 6.02 Full Scale Amplitude Actual Input Amplitude
This is the time required before the A/D output data is valid once the analog input is back within the specified range. This time is only guaranteed if the input does not exceed 4.75V (bipolar) or +2 to -7.5V (unipolar). The minimum supply voltages of +4.9V and -4.9V for VDD are required for -55C operation only. The minimum limits are +4.75V and -4.75V when operating at +125C.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-932 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 7, 30 and 36) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +3.2V reference output to ground with 4.7F tantalum capacitors in parallel with 0.1F ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-932 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warm-up. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3 3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the ADS-932 (see Tables 2a and 2b). When this pin has a TTL logic "0" applied, it complements all of the ADS-932's digital outputs. Pin 35 is TTL compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 35 allowing it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a logic "0" (low). To disable, connect pin 34 to a logic "1" (high). 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. Data from both the interrupted and subsequent conversions will be invalid.
ADS-932
6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the rising edge of EOC to the falling edge of EOC). 7. The OVERFLOW bit (pin 33) switches from 0 to 1 when the input voltage exceeds that which produces an output of all 1's or when the input equals or exceeds the voltage that produces all 0's. When COMP BITS is activated, the above conditions are reversed. 8. When configuring the ADS-932 for the unipolar mode, Pin 1 (+3.2V REF.) should be connected to Pin 2 (Unipolar) through a non-inverting op-amp. For precision DC applications an OP-07 type amplifier is recommended, while AC applications requiring the lowest level of harmonic distortion should consider the AD9631. When configuring the ADS-932 for the bipolar mode, Pin 2 (Unipolar) should be physically disconnected from the surrounding circuitry. This will help prevent noise from coupling into the A/D.
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When the FIFO is initially empty, digital data from the first conversion (the "oldest" data) appears at the output of the FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 34), data from the first conversion will appear at the output of the ADS-932. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. After the 15th rising edge brings the 16th data word to the FIFO output, the subsequent falling edge on READ will update the status outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating that the FIFO is empty. If a read command is issued after the FIFO empties, the last word (the 16th conversion) will remain present at the outputs.
INTERNAL FIFO OPERATION
The ADS-932 contains an internal, user-initiated, 18-bit, 16word FIFO memory. Each word in the FIFO contains the 16 data bits as well as the MSB and overflow bits. Pins 8 (FIFO/ DIR) and 9 (FIFO READ) control the FIFO's operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1) and 11 (FSTAT2). When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the digital data path. When pin 8 has a logic "0" applied, the FIFO is transparent and the output data goes directly to the output three-state register (whose operation is controlled by pin 34 (ENABLE)). Read and write commands to the FIFO are ignored when the ADS-932 is operated in the "direct" mode. It takes a maximum of 20ns to switch the FIFO in or out of the ADS-932's digital data path.
FIFO Reset Feature
At any time, the FIFO can be reset to an empty state by putting the ADS-932 into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs change 40ns after applying the control signals.
FIFO Status, FSTAT1 and FSTAT2
Monitor the status of the data in the FIFO by reading the two status pins, FSTAT1 (pin 10) and FSTAT2 (pin 11).
CONTENTS Empty (0 words) FIFO Write and Read Modes
Once the FIFO has been enabled (pin 8 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO.
DELAY Direct mode to FIFO enabled FIFO enabled to direct mode FIFO READ to output data valid FIFO READ to status update when changing from Table 1. FIFO Delays TRANSITION 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 MIN. - - - - - - - - - TYP. 10 10 - - - - - - - MAX. 20 20 40 20 110 190 190 110 28 UNITS ns ns ns ns ns ns ns ns ns
0 0 0
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ADS-932
12) so that the converter is continuously converting. 2. For unipolar or bipolar zero/offset adjust, apply -42V to the ANALOG INPUT (pin 3). 3. For bipolar inputs, adjust the offset potentiometer until the code flickers between 1000 0000 0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (complementary offset binary) or between 0111 1111 1111 1111 and 1000 0000 0000 0000 with pin 35 tied low (offset binary). For unipolar inputs, adjust the offset potentiometers until all output bits are 0's and the LSB flickers between 0 and 1 with Pin 35 tied high (straight binary) or until all bits are 1's and the LSB flickers between 0 and 1 with pin 35 tied low (complementary binary). 4. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the trimpot until the output code flickers between all 0's and all 1's.
CALIBRATION PROCEDURE
Connect the converter per Figure 2. Any offset/gain calibration procedures should not be implemented until the device is fully warmed up. To avoid interaction, adjust offset before gain. The ranges of adjustment for the circuits in Figure 2 are guaranteed to compensate for the ADS-932's initial accuracy errors and may not be able to compensate for additional system errors. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-932, offset adjusting is normally accomplished when the analog input is 0 minus 1/2 LSB (-42V). See Table 2b for the proper bipolar output coding. Gain adjusting is accomplished when the analog input is at nominal full scale minus 11/2 LSB's (+2.749874V). Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain adjustment.
Gain Adjust Procedure
1. Apply +2.749874V to the ANALOG INPUT (pin 3). 2. For bipolar inputs adjust the gain potentiometer until all output bits are 0's and the LSB flickers between a 1 and 0 with pin 35 tied high (complementary offset binary) or until all output bits are 1's and the LSB flickers between a 1 and 0 with pin 35 tied low (offset binary). 3. Two's complement coding requires using BIT 1 (MSB) (pin 29). With pin 35 tied low, adjust the gain trimpot until the output code flickers equally between 0111 1111 1111 1111 and 0111 1111 1111 1110.
Zero/Offset Adjust Procedure
1. Apply a train of pulses to the START CONVERT input (pin
20k +5V -5V +5V
20k -5V
6 GAIN ADJUST +5V 4.7F 0.1F 31 +5V DIGITAL
5 OFFSET ADJUST
DIGITAL 7, 30 GROUND
33 OVERFLOW 32 EOC 29 BIT 1 (MSB) 28 BIT 1 (MSB) 27 BIT2 26 BIT 3 25 24 23 22 BIT 4 BIT 5 BIT 6
+
+5V 4.7F
38 0.1F
+5V ANALOG
ANALOG 4, 36 GROUND
-5V
4.7F
0.1F
37
-5V
ADS-932
34 8 CONNECT for UNIPOLAR MODE 10 2 6.8F 11 1 0.1F 4.7F
ENABLE FIFO/DIR FSTAT1 ANALOG INPUT UNIPOLAR FIFO READ FSTAT2 +3.2V REF. OUT START CONVERT 12 COMP. BITS 35 9 3
BIT 7 21 BIT 8 20 BIT 9 19 BIT 10 18 BIT 11 17 BIT 12 16 BIT 13 15 BIT 14 14 BIT 15 13 BIT 16 (LSB)
+
+5V
Figure 2. Bipolar Connection Diagram
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ADS-932
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70C and -55 to +125C. All room-temperature (TA = +25C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally-conductive "pads" may be installed
N START CONVERT 100ns typ. Acquisition Time 225ns typ. 275ns typ. N+1
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underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters," or contact DATEL directly, for additional information.
N+2 N+3
20ns typ. INTERNAL S/H Hold
75ns typ. EOC 260ns typ. Conversion Time 20ns typ. OUTPUT Data N-4 Valid DATA
45ns typ.
440ns typ. Data N-3 Valid 60ns typ. Invalid Data Data N-2 Valid Invalid Data Data N-1 Valid
Notes: 1. Scale is approximately 50ns per division. fs = 2MHz. 2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the first conversion to appear at the output of the A/D. 3. The start convert positive pulse width must be between either 40 and 175nsec or 280 and 460nsec (when sampling at 1MHz) to ensure proper operation. For sampling rates lower than 1MHz, the start pulse can be wider than 460nsec, however a minimum pulse width low of 40nsec should be maintained. A 1MHz clock with a 100nsec positive pulse width is used for all production testing.
Figure 3. ADS-932 Timing Diagram
0 -10 -20 Amplitude Relative to Full Scale (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0 100 200 300 400 500 600 700 800 900 1000
Frequency (kHz) (fs = 2MHz, fin = 975kHz, Vin = -0.5dB, 16,384-point FFT)
Figure 4. FFT Analysis of ADS-932
6
R1 +5VA +5VF C15 0.1F 20 9 U2 8 7 DGND -15V C2 2.2F 5 AGND 4 DGND 0.1F 0.1F B1(MSB) B2 B3 B4 20 9 8 B2 B3 B4 B5 17 18 19 11 AB3 AB4 AB5 AB6 AB7 AB8 DGND AB16 AB15 AB14 AB13 L3 -5VA 74HC86 4 6 START U5 CONVERT 5 20mH AB12 AB11 AB10 10 L4 +5VA GAIN ADJUST +5VA 1 AGND 3 -5VA OFFSET ADJUST 2 R4 20k 2 3 -5VA 1 R5 20k DGND +5VA 20mH C13 2.2F 9 +5VF 13 12 14 U5 11 FST1 7 74HC86 DGND C8 0.1F DGND +5VF DGND 74HC86 8 U5 FST2 AB9 9 8 7 6 5 4 3 2 11 1 U4 C17 0.1F 20 10 12 13 14 15 16 17 18 19 1 B9 B6 B10 B7 B11 B8 B12 B13 B14 8 DGND B16 (LSB) B15 B14 B13 B12 B11 B10 B9 FIF +5VD COMP 123 RD 123 J5 FIFO/DIR J4 READ 1 2 3 J2 1 2 3 J3 ENABLE COMPLIM
74HCT573
R2 SG7 +15V 12 13 14 15 16 17 AGND AGND DGND 18 OVRFLW 19 B1B MSB 11 1 C18 0.1F C19 0.1F C20 0.1F C14 2.2F C12 2.2F +5VD -5VA +5VA +5VD -5VA +5VA C21 2.2F C1 2.2F 6 -5VA SG8 6
74HCT573
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AGND C3 0.1F C4 2.2F
10
DGND
2
7
AMPLIFIER OPTION
AR1
3
4
ANALOG INPUT UUT 1 +3.2VREF 2 +5VF SG5 AGND 3 ANA IN 4 AGND 4 5 U1 6 7 2 1 FIF DGND RD READ 10 FSTAT1 DGND FSTAT2 12 START AB16 LSB 14 B15 15 B14 16 B13 17 B12 18 B11 19 B10 20 B9 U6 B8 21 B7 22 B6 23 B5 24 B4 25 B3 26 B2 AB2 +5VF 27 AB8 2 AB15 L1 +5VF C7 2.2F DGND +5VD AB10 20mH AB9 C9 2.2F L2 AB11 AB12 20mH AB13 AB14 13 MSB AB1 28 AB7 3 MSB 29 AB6 4 DGND 11 30 AB5 +5VD 5 16 31 +5VD AB4 6
74HCT573
B2 SG6 AGND NC NC +5VA -5VA 37 AGND COMP COMP AB1 U3 13 14 15 B1 (MSB) AB2 DGND AB3 7 12 ENABLE OF EOC 32 33 34 35 10 DGND B5 B6 24 B7 22 B8 20 36 C16 0.1F -5VA 38 +5VA +5VF 39 2 34 32 30 28 26 SG9 AGND 40 3
AGND
AGND
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2
AGND +5VF
33 31 29 27 25 23 21 19 P1 18 16 14 17 15 13 12 11 10 9 7
B1B MSB OVRFLW EOC DGND DGND DGND DGND DGND
10 5 OFFSET AGND 6 GAIN R3 8 FIFO/DIR 9 3.3k DGND
14
C5
12
0.1F
11
74HCT74
U1
9
2
74HCT74
8
DGND
7 1 2 C10 1 33pF
13
3
DGND
+5VF
1
X1
14
C6 2.2F
7
2MHZ
8
DGND
DGND DGND ENABLE COMPLIM N.C. READ B15 6 B16 (LSB) 4 START 2 1 3 FST2 5 FST1 FIF/DIR DGND
START CONVERT
J1
7
C11 2.2F AGND 74HC86 1 3 U5 EOC 2
1
B1
R6
321
50
+5VD
-5VA
DGND
-15V
26 24 22 20 18 16 14 12 10 8 6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
+15V DGND +5VA
P2
SG1
SG2
SG3
SG4
AGND
DGND
ADS-932 EVALUATION BOARD
ADS-932
Figure 5. ADS-932 Evaluation Board Schematic.
ADS-932
Table 2a. Setting Output Coding Selection (Pin 35)
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OUTPUT FORMAT
Complementary Offset Binary Offset Binary
PIN 35 LOGIC LEVEL
1 0 1 0 1 0
Complementary Two's Complement (Using MSB, pin 29) Two's Complement (Using MSB, pin 29) Straight Binary Complimentary Binary
Table 2b. Output Coding
STRAIGHT BINARY
COMP. BINARY
UNIPOLAR SCALE
-FS+1 LSB -FS +1 1/2 LSB -7/8 FS -3/4 FS -1/2 FS -1/2FS-1/2LSB -1/4 FS -1/8 FS -1 LSB -1/2 LSB 0
INPUT RANGE 0 to -5.5V
-5.499916 -5.499874 -4.812500 -4.125000 -2.750000 -2.749958 -1.375000 -0.687500 -0.000084 -0.000042 0.000000
OUTPUT CODING MSB LSB
1111 0000 0000 0000 1111 0000 0000 0001 0000
MSB
LSB
0000 1111 1111 1111 0000 1111 1111 1110 1111
MSB
0111 0110 0100 0000 1111 1100 1010 1000 1000
LSB
1111 1111 LSB "1" to "0" 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 1111 0000 0000 0000 1111 0000 0000 0001 0000
MSB
1000 1001 1011 1111 0000 0011 0101 0111 0111 0000 0000 LSB "0" to "1" 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111
LSB
0000 1111 1111 1111 0000 1111 1111 1110 1111
INPUT RANGE 2.75V
+2.749916 +2.749874 +2.062500 +1.375000 0.000000 -0.000084 -1.375000 -2.062500 -2.749916 -2.749958 -2.750000
BIPOLAR SCALE
+FS -1 LSB +FS -1 1/2 LSB +3/4 FS +1/2 FS 0 -1 LSB -1/2 FS -3/4 FS -FS +1 LSB -FS + 1/2 LSB -FS
1111 1111 1111 LSB "1" to "0" 1110 0000 0000 1100 0000 0000 1000 0000 0000 0111 1111 1111 0100 0000 0000 0010 0000 0000 0000 0000 0000 LSB "0" to "1" 0000 0000 0000
0000 0000 0000 LSB "0" to "1" 0001 1111 1111 0011 1111 1111 0111 1111 1111 1000 000 000 1011 1111 1111 1101 1111 1111 1111 1111 1111 LSB "1" to "0" 1111 1111 1111
OFFSET BINARY
COMP. OFF. BIN.
TWO'S COMP.
COMP. TWO'S COMP.
Table 3. Input Connections
Input Range
0 to -5.5V 2.75V
Input Pin
Pin 3 Pin 3
Connect
Pin 1 To Pin 2 Pin 2 is No Connect
8
(R)
(R)
ADS-932
0.74
Number of Occurrences
-0.56 0 Codes 65,536
0
DNL (LSB's)
Digital Output Code Figure 6. ADS-932 Histogram and Differential Nonlinearity
65,536
4410
4000
3000
2000
1000
0 Digital Output Code Figure 7. ADS-932 Grounded Input Histogram This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-932.
9
ADS-932
MECHANICAL DIMENSIONS INCHES (mm)
(R)
(R)
2.12/2.07 (53.85/52.58)
40
21
Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) 0.010 (0.254) 3 place decimal (.XXX) 0.005 (0.127) Lead Material: Kovar alloy
1.11/1.08 (28.20/27.43)
Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating
1
20
0.100 TYP. (2.540) 1.900 0.008 (48.260) 0.245 MAX. (6.223)
PIN 1 INDEX ( ON TOP)
0.200/0.175 (5.080/4.445)
0.015/0.009 (0.381/0.229) 0.210 MAX. (5.334) 0.018 0.002 (0.457) 0.045/0.035 (1.143/0.889) 0.110/0.090 (2.794/2.286) SEATING PLANE 0.035/0.015 (0.889/0.381) 0.900 0.010 (22.86) 0.110/0.090 (2.794/2.286
ORDERING INFORMATION
OPERATING TEMP. RANGE 0 to +70C -55 to +125C
MODEL ADS-932MC ADS-932MM
ACCESSORIES ADS-B932 HS-40 Evaluation Board (without ADS-932) Heat Sink for all ADS-932 models
Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.
(R)
(R)
ISO 9001
R E G I S T E R E D
INNOVATION and EXCELLENCE
DS-0308A
01/2000
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000, (800) 233-2756 Fax: (508) 339-6356 Internet: www.datel.com E-mail: sales@datel.com Data sheet fax back: (508) 261-2857
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 Munchen, DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

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